The present invention relates to a class D audio power amplifier and is specifically directed to output DC offset protection.
In every amplification system, a standard design specification goal is the protection circuits and one of these is the output DC offset protection. DC offset voltage is defined as the DC output voltage when there is no applied voltage at the input. These can be due to mismatch of the elements or may be due to some component degradation over time, electrical overstress of the IC and any other means that will translate into a DC offset at the output of the amplifier causing large current to the speakers which may cause damage. It has also been observed that the large DC current dissipation on speaker give rise to a risk of fire. As this posed a serious issue on safety, techniques have been proposed to minimize the occurrence of this problem.
An example of such a technique was discussed in U.S. Pat. No. 7,078,964 titled DETECTION OF DC OUTPUT LEVELS FROM A CLASS D AMPLIFIER filed Oct. 12, 2004. In this prior art as seen in FIG. 1 and FIG. 2. a class D audio amplifier system 6 with DC output detection logic 4 was disclosed. The amplifier system 6 includes a multiple audio channels 7, each of which includes a pulse-width-modulator 9. The DC detection logic 4 includes a sigma-delta modulator and a digital low-pass filter that monitors the PWM output signals from the PWM modulators. The sigma-delta modulator operates at a first clock frequency, while the low-pass filter operates at a much lower clock frequency, so that AC audio components, PWM harmonics, and sigma-delta quantization error is suppressed from the DC detection. The modulated filtered signal is compared against a threshold level to determine whether the amplitude of the DC component at the PWM output is sufficiently high enough to constitute a fault. If so, a fault detection signal is issued, and the PWM modulators are disabled to prevent unsafe condition in the system. Such technology may be disadvantageous due to the fact that it detects offset at the PWM stage. The offset contributed by the succeeding stages are not taken into account such as the offset due to dead time, or due to the delay incurred by the parasitic capacitances at the output stages.